V-by-One® HS FPGA IP

Description

V-by-One-HS.pngThe V-by-One®HS is a leading-edge high speed interface technology which THine Electronics, Inc. developed and specified for Flat Panel Display markets.

Implementing the V-by-One®HS Functional IP on to Altera FPGAs that Mpression offers enables the FPGA based V-by-One® HS technology to offer higher frame rates and higher resolutions for FPDs. The IP has 2 kinds, the transmitter IP and the receiver IP. This makes it possible to reduce the cost considerably comparing with the conventional technology like LVDS.

Features

  • Maximum transfer rate per lane is 4 Gbps. (Depends on the FPGA the IP implemented.)
  • Verified ALTERA FPGA:
  • Applicable for not only VESA/SMPTEstandard video formats but also any user custom formats.
  • Flexible multiple lane configurations according to the requirements of the transfer rates.
  • Built in Self Test called FieldBETto check the connection between the transmitter IP and the receiver IP.

Specification

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Recommendation of pixel resolutions and number of lanes

v-by-one-resolutions.jpg

License Package

  • Encrypted RTL (Verilog-HDL)
  • Sample design of the IP implementation for your reference
  • Simulation environment (For Modelsim)
  • Design manuals (User's manual, Reference manual, Simulation manual)

Block Diagram

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Circuit Resource

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Functional IP(VX1 TX)　:　V-by-One®HS Functional IP(Transmitter）
Functional IP(VX1 RX)　:　V-by-One®HS Functional IP(Receiver）

*Circuit resource in the above table are just reference numbers for your estimation. (MAP mode is OFF.)

*All company names and product names mentioned are registered trademarks, trademarks or service marks of the respective companies.